The invention relates to a display driving apparatus outputting a driving signal to a display, and in particular relates to a display driving apparatus for driving a plasma display panel.
In recent years, display apparatuses such as television receivers and so on tend to be large in size and thin, and also plasma display panels (hereinafter referred to as PDPs) are used widely. As a driving apparatus for driving the PDP, the driving apparatus using a MOS transistor in an output stage is proposed (see, for example, paragraph numbers [0001]˜[0010] and [0026]˜[0039], and FIGS. 1 to 3 and FIG. 9 in Japanese Patent Application Publication No. 2005-176298, which corresponds to United States Patent Application Publication No. US2005/0036950A1 and Korean Patent Application Publication No. 2005/014672). FIG. 3 is a view schematically showing an example of the constitution of a PDP driving apparatus.
The PDP driving apparatus shown in FIG. 3 has a plurality of scan drivers SD1 to SDn and data (address) drivers DD1 to DDm for driving a two-electrode PDP (here, n and m are positive integers). The scan drivers SD1 to SDn respectively drive a plurality of scanning (sustaining) electrodes, and the data drivers DD1 to DDm respectively drive a plurality of data electrodes corresponding to each color of R (red), G (green) and B (blue). These scanning electrodes and data electrodes are arranged in a grid so as to be perpendicular to one another, and discharge cells, not shown, are disposed at the points of intersection therebetween.
In the PDP driving apparatus of the configuration, data from the data electrodes are written into the discharge cells while scanning through every scanning electrode by the scan drivers SD1 to SDn and the data drivers DD1 to DDm, and discharge sustaining pulses are output to the scanning electrodes to sustain the discharges for a predetermined period, whereby an image is displayed.
FIG. 4 is a view showing the circuit configuration of an output stage in a conventional display driving apparatus for driving one scan line in the scan drivers SD1 to SDn. The display driving apparatus has two n-channel type IGBTs (Insulated Gate Bipolar Transistors) Q101 and Q102 which are connected in series. The IGBT Q101 which is a high-side output element is driven by a level shifter circuit 101, and the IGBT Q102 which is a low-side output element is driven by a buffer circuit which consists of an inverter IC 101 and a totem-pole circuit of two n-channel type MOS transistors NT101 and NT102 connected in series. In addition, a connecting point of the two IGBTs Q101 and Q102 is connected to an output terminal T0.
A high-side diode D101 and a low-side diode D102 are connected to the IGBT Q101 and the IGBT Q102 in parallel respectively. Moreover, a resistor R101 and a Zener diode ZD101 are connected to a gate of the IGBT Q101, and a Zener diode ZD102 is connected to a gate of the IGBT Q102.
In a circuit shown in FIG. 4, the IGBT Q101 is controlled by a signal of a high voltage VDH so that a signal of a low voltage VDL of 0 to 5 volts is converted into the signal of the high voltage VDH of 0 to 100 volts by a level shifter circuit 101, and the IGBT Q102 is controlled by the buffer circuit constituted from the totem-pole circuit of the MOS transistors NT101 and NT102.
The reason why the buffer circuit controlling the IGBT Q102 is constituted from the totem-pole circuit of the MOS transistors NT101 and NT102 is to make a drop in an output waveform gradual during the address discharge and to prevent the output voltage of the IGBT Q102 from becoming high by making the gate voltage of the IGBT Q102 higher than the low voltage power supply VDL through a parasitic capacitance C101 and increasing the drive capability of the IGBT Q102 when the output voltage of the IGBT Q102 became high in operation. At this time, the gate voltage of the IGBT Q102 is clamped at about 7 volts due to a Zener diode ZD102.
Furthermore, a driving signal of a high voltage of 100 volts is output from the above circuit to the scanning electrodes and the discharge cells of the PDP, but it is necessary to reduce the potential of the output terminal To to 0 volt by turning the IGBT Q102 on at the time of the address discharge. To do this, a signal of an input terminal Ti is made to be L (low level) and the output of the buffer circuit is made to be H (high level), and the IGBT Q102 is turned on. As a result, 0 volt, i.e. the same potential as the reference power supply potential GND is output to the output terminal To. About 3 volts, which is lower than the low voltage VDL, is applied to the gate of the IGBT Q102 at this time. The reason for this will be explained as follows with reference to FIG. 5.
FIG. 5 is a cross-sectional view schematically showing the structure of the MOS transistor NT101 in the buffer circuit. The MOS transistor NT101 comprises a p well 11 formed on a substrate 10, a drain electrode 12 and a source electrode 13 which are formed by implanting the impurity of an n+ type into the surface of the p well 11, a gate oxide film 14 and a gate electrode 15 formed on the gate oxide film 14.
When 5 volts is applied to the gate electrode 15 in the MOS transistor NT101, the MOS transistor NT101 becomes an on-state due to a channel formed. In this configuration, the MOS transistor NT101 functions as a source follower circuit and approximately the voltage applied to the gate electrode being subtracted from the threshold voltage of the MOS transistor NT101 is output from the source electrode 13. The p well 11 is 0 volt at this time, and the threshold voltage is increased by a back gate effect (a substrate effect). When 5 volts is applied to the drain electrode 12 by the low voltage VDL, the potential of source electrode 13 becomes about 3 volts. Because the source electrode 13 is connected to the gate of the IGBT Q102, about 3 volts lower than the low voltage VDL is supplied to the gate of the IGBT Q102.
FIG. 6 is a timing diagram showing part of current and voltage wave forms during the address discharge, and shows the wave forms of the gate voltage of the MOS transistor NT102, the gate voltages of IGBT Q101 and IGBT Q102 and the output voltage Vo (the potential of the output terminal To) respectively.
When changing an input voltage to L level at time t1, a gate voltage of the IGBT Q101 drops from the high voltage VDH to the ground potential GND and also the gate voltage of the MOS transistor NT102 in the buffer circuit drops to the ground potential GND, so the gate voltage of the IGBT Q102 rises to a voltage of about 3 volts, which is lower than the low voltage VDL, and the IGBT Q102 becomes the on-state after turning on. When the IGBT Q102 turns on in this way, the wave form in a drop of the output voltage Vo is more gentle than that in the case that the gate voltage of the IGBT Q102 is the low voltage VDL, and the potential of the output voltage Vo becomes 0 volt at time t2. At this time, a current Ip due to charge stored in the discharge cell of the PDP connected to the output terminal To does not flow rapidly and flows to the ground terminal connected to an emitter of the IGBT Q102 in accordance with the period up to the time t2. After the output voltage Vo becomes 0 volt, once the effective voltage due to a high voltage applied to the data electrodes of the PDP at time t3 has become sufficiently high, a plasma discharge is started, and hence a discharge current Ih flows. The discharge current Ih finishes flowing at time t4.
In the course of operation, because the discharge current Ih rapidly flows through a collector of the IGBT Q102 at the time of the address discharge, the gate voltage of the IGBT Q102 rises due to the drain-gate capacitance, i.e. the parasitic capacitance C101 of the IGBT Q102, and the output voltage Vo is raised accordingly. The gate of the IGBT Q102 rises to about 5 volts which is approximately the same as the low voltage VDL hereby and large current flows instantaneously. This makes a stable display.
In this way, without suppressing the discharge current, a drop in the output waveform during the address discharge can be made gentle, whereby noise can be prevented. Moreover, because current supply capacity is suppressed, the element can be prevented from being damaged due to an excessive current upon a short-circuiting of an output. However, when, for example, in the conventional display driving apparatus configured as above, ESD (electrostatic discharge) is applied to the output terminal by a positive charge as against the ground potential in an outgoing test or an acceptance test, the positive charge usually flows to a power line of the high voltage through the high-side diode. But when ESD is repeatedly applied to the output terminal, the low-side IGBT is turned on at the time of ESD applied because the charge is stored in the gate of the low-side IGBT. Because of this, as shown in a dotted line with an arrow of FIG. 4, there has been a problem that the charge of ESD flows through only the low-side IGBT and this makes the element prone to damage.
In view of such a problem, it is an object of the invention to provide a display driving apparatus wherein the low-side output transistor can be prevented from being damaged without charge stored in the gate of the low-side output transistor even if ESD is repeatedly applied to the output terminal by the positive charge as against the ground potential.
Further objects and advantages of the invention will be apparent from the following description of the invention.